Undergraduate and dissertation project (m / f / d) Zonal communication architecture for robotic hands

DLR dlr.de Open · verified Sep 18, 2026

Oberpfaffenhofen Mid-level Communications

Mid-level Communications role at DLR. Oberpfaffenhofen.

Role brief

Growth Roles summary, based on the employer's posting.

What you'll do

Analyze data-transfer needs for cameras, sensors, and actuators
Add hardware protocol IP cores to FPGA development boards
Create VHDL gateway logic connecting SPI, I2C, and MIPI
Build a working demonstrator for hardware data transmission
Measure and verify latency and throughput across the full data path

What you bring

Strong hands-on experience using Xilinx Vivado
Deep VHDL knowledge for logic development and IP integration
Skills in digital electronics, prototyping, and hardware debugging

Who this fits

This role suits you if you are pursuing an undergraduate or dissertation project in robotics hardware. You will work on communication architecture for robotic hands at DLR's Oberpfaffenhofen site. The work centers on FPGA development, digital electronics, and hands-on validation.

From the employer

The Institute of Robotics and Mechatronics develops robots that enable people to interact with the environment more efficiently, effectively and safely. The robots are designed to work in environments that are inaccessible or dangerous for humans, but also to support and relieve people at work and in everyday life.

What to expect

Robotics in the field of humanoid service robots aims to automate dangerous tasks.
Various bipedal systems are being developed at the German Aerospace Centre that are intended to approximate their biological counterparts in terms of performance.
Integrated legs, arms, hands and upper body are being developed to realise these highly developed systems.
The development process includes the design, assembly, commissioning and comprehensive testing of the systems..

Your tasks

analysing data flow requirements for cameras, sensors and actuators
integrating hardware protocol IP cores onto FPGA development boards
developing gateway logic in VHDL to bridge SPI, I2C and MIPI
building a functional hardware demonstrator for data transmission
measuring and validating end-to-end latency and data throughput

Your profil

very good practical experience with Xilinx Vivado
in-depth knowledge of VHDL for logic design and IP integration
proficiency in digital electronics, prototyping and hardware debuggi

We look forward to getting to know you!

If you have any questions about this position (Vacancy-ID 5979) please contact:

Dr. Markus Grebenstein
Tel.: +49 8153 28 1064