RTL-to-GDS implementation, Senior Principal Solutions Engineer
Cadence Open At a glance
Senior Solutions & Sales Engineering role at Cadence. Austin · full-time · no salary stated · we estimate $158,375–$211,533.
Cadence has not published a salary for this role. The figure below is our estimate, not theirs.
growthroles summary, based on the employer's posting.
What you'll do
- Help chip designers adopt Cadence tools to meet their performance, power and area goals
- Support RTL-to-GDS project delivery, including block, top-level and signoff implementation work
- Explain design methods using Cadence tools and build fluency across its tool portfolio
- Run customer evaluations and benchmarks of front-end solutions to show where the technology stands apart
- Balance several technical issues, set priorities and apply new technologies to customer work
What you bring
- At least seven years of experience and strong technical command of the company’s products
- Hands-on ASIC design using Verilog or another industry-standard hardware description language
- Deep experience with Cadence or Synopsys place-and-route tools, including physical synthesis, CTS and static timing analysis
- Experience supporting RTL-to-GDS implementation flows with the Encounter Digital Implementation Platform
Who this fits
This senior applications engineering role suits someone with deep place-and-route expertise who can support customer implementations and technical evaluations. You’ll work with wireless and mobile customers on low-power and multi-voltage design techniques.
From the employer
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable.
In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you.
Position Requirements:
* 7+ years experience and a strong technical knowledge of company products.
* Design experience should include ASIC design using industry-standard hardware description languages (Verilog)
* Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required
* Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers
* Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform
* Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position
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